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DFT ATPG DESIGN ENGINEER COOP (CPU):

DESCRIPTION OF POSITION:
The candidate will be a coop engineer working on ATPG, Structural Test, & scanDFT aspects of leading-edge process technology, multi-GHz microprocessor designs. Our candidate will gain experience in developing and validating structural test features to meet product testability, diagnostic and quality requirements.

SPECIFIC JOB FUNCTIONS:
Develop and validate structural modes, test protocols and process flows to ensure thorough structural quality targets. Utilize ATPG tools to analyze and drive closure on structural coverage goals. Work to streamline the design validation process and test feature operation to reduce cost of test. Explore and productize the latest testability tools/technologies.

REQUIRED EDUCATION AND EXPERIENCE:

• Junior or Senior candidate for MS in Electrical Engineering, Computer Engineering, or ECE
• Prior exposure to ATPG tools, fault coverage, fault simulation techniques, scan design, hardware compression techniques, and/or BIST
• Optional but preferred skills that add value are:
  • Scripting languages – Python, Ruby, Perl, TCL, or Shell
  • Physical Design, Synthesis, and Electrical Rule Checking
  • Debug and Waveform analysis; Simulation based Diagnostics
  • Circuit Design, Logic Design
  • RTL coding in Verilog or VHDL
  • Microprocessor architecture
  
  

Requisition Number: 182392
Country: United States State: California City: Santa Clara
Job Function: Student/ Intern/ Temp

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.